Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to providing a pass-through based architecture.
Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a 3-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure.
FinFET designs use “fins” that may be formed on the surface of a semiconductor wafer using selective-etching processes. The fins may be used to form a raised channel between the gate and the source and drain of a transistor. The gate is then deposited such that it wraps around the fin to form a trigate structure. Since the channel is extremely thin, the gate would generally have a greater control over the carriers within. However, when the transistor is switched on, the shape of the channel may limit the current flow. Therefore, multiple fins may be used in parallel to provide greater current flow for increased drive strength.
FIG. 1 illustrates a stylized cross-sectional depiction of a state-of-the-art FinFET device. A FinFET device 100 illustrated in FIG. 1 comprises a plurality of “fins” 110. The semiconductor device may be position to a vertical orientation, creating one or more fins 110. The source and drain of the FinFET are placed horizontally along the fin. A high-k metal gate 120 wraps over the fin, covering it on three sides. The gate 120 defines the length (labeled L) of the FinFET device. The current flow occurs along an orthogonal crystal plane in a direction parallel to the plane of the semiconductor wafer. The electrically significant height of the fin (labeled H) is typically determined by the amount of oxide recess in the fin reveal step and hence is constant for all fins 110.
The thickness of the fin (labeled Tfi) determines the short channel behavior of the transistor device and is usually small in comparison with the height H of the fin 110. The pitch (labeled P) of the fins is determined by lithographic constraints and dictates the wafer area to implement the desired device width. A small value of the pitch P and a large value of the height H enable a better packing of the devices per square area resulting in a denser design, or more efficient use of silicon wafer area.
The scaling down of integrated circuits coupled with higher performance requirements for these circuits have prompted an increased interest in finFETs. FinFETs generally have the increased channel widths, which includes channel portions formed on the sidewalls and top portions of the fins. Since drive currents of the finFETs are proportional to the channel widths, finFETs generally display increase drive current capabilities.
Designers are constantly attempting to increase the density of integrated circuits by decreasing the size of features on semiconductor devices. As a result, there is challenge to create standard functional cell library logic devices, such as scan-D flip-flops and multiplexers to accommodate the smaller devices. This is particularly the case at the 10 nm node, where lithographic limitations can result in a lack of scaling of standard cell library devices. One solution attempted by designers is to perform cross coupling of transistors for providing standard cell library devices. Cross coupling and logic scaling provides for utilizing lower amount of area of the semiconductor device, in an attempt to overcome undesirable properties, such as larger semiconductor device or less functionality in the semiconductor device.
As finFET devices become more dense (e.g., 10 nm technology), the tracks (i.e., metal pitch) become smaller. This raises many issues, such as processing accurately at 7.5 nm track (7.5T) spaces. In a 7.5T design, in a standard cell, at 42 nm spacing per track, only 315 nm are generally available. Generally 42 nm is typically selected as a limit to allow for printing Self-Aligned Double Patterns (SADP) at various sizes, as would be required for Static Random Access Memory (SRAM) Metal 2 (M2) Word Lines (WL) and potential sizing usage in logic routing levels.
Designers often use pre-designed basic cells to form layouts of more complex cells comprising finFET devices (e.g., flip-flops). In a CMOS integrated circuit, PMOS and NMOS transistor pairing are often used to form circuit cells. For example, FIG. 2 illustrates a stylized cross-sectional depiction of a state-of-the-art cell design. The PMOS region 201 of the cell 200 comprises a plurality of PMOS full stripe source/drain (S/D) contacts 210. The NMOS region 202 comprises a plurality of NMOS full stripe S/D contacts 212. Further, the cell 200 comprises a plurality of gates 230.
In order to tie some features of the cell 200, e.g., gates, to power signals (VDD and VSS), power rails may be formed. Generally, the source or the drain contacts are also connected to power signals using the power rails. In the example of FIG. 2, a PMOS source contact 232 is connected to VDD power rail through a CA via connection. Similarly, an NMOS source contact 252 is connected to VSS using the power rail 265 through a CA via connection.
Often, a circuit design may call for connecting a portion of the S/D regions 270 of the PMOS region 201 to the S/D regions 270 of the NMOS region 202. As shown in FIG. 2, a cell 200 comprises a plurality of C-shaped M1 structures (240a, 240b, 240c, collectively “240”). The C-shaped structures 240 are used to provide a connection between a portion of the PMOS region 201 (e.g., S/D fins 270) and a portion of the NMOS region 202 (e.g., S/D fins 265). As described below, the C-shaped structures 240 may cause various problems. A more simplified description of the C-shaped structures 240 is provided in FIG. 3 below.
FIG. 3 illustrates a stylized depiction of a typical C-shaped structure in a cell 300. The cell 300 comprises a plurality of PC (gate) formations 310. A plurality of CB metal formations 350 may be used to connect up some gates 310 to formations in other/upper metal layer. The cell 300 includes a 1st active region 320 (e.g., NMOS region) and a 2nd active region 330 (e.g., PMOS region. The cell 300 may also comprise a 1st CA formation 360 and a 2nd CA formation 365. The 1st CA formation 360 may be connected to the active region 320 using a via 361, and the 2nd CA formation 365 may be connected to the active region 330 using a via 366. The 1st CA formation 360 from the NMOS region may be connected to the 2nd CA formation 365 by using a C-shaped M1 formation, wherein the C-shape is used to route around the CB formations 350.
In some cases, there may be instances where for routing around certain structures, a C-shape structure 240b may be formed. In some cases, other routing issues may prompt a designer to place another, larger C-shape structure 240a, which may envelop the C-shape structure 240b (as shown in FIG. 2). In this case, unidirectional metal structures (M0/M1) may be used to accommodate routing around these nested C-shape structures 240. However, this approach is often problematic because of via enclosures and metal line (M0) tip-to-tip limits.
The C-shaped structures 240 may cause various process issues. For example, usage of the C-shaped structures 240 requires more space, and thus, causes the cell 200 to become taller. This causes the integrated circuit formed using the cell 300 to be larger, and increases power consumption. Further, formation of the C-shaped structures 240 can cause lateral connection problems. Also, more silicon would be required at the corners of the C-shaped structures 240, which could cause process errors. Further, the C-shaped structures 240 cause various routing congestion problems.
Designers have attempted to alleviate some of the problems with C-shaped structures 240 by reducing the number of C-shaped structures 240 being used by providing a CA pass-through formation 440, which passes through the cell from the PMOS active region 330 to the NMOS region 320. FIG. 4 illustrates a stylized depiction of a cell 400 that includes a CA pass-through formation. The CA formation 440 is formed between gates 310. The CA formation 440 is generally formed using self-aligned contact (SAC) formation process. As such, the CA formation 440 tends to be upsized.
As a result of the size of the CA pass-through 440, the CB formations have to be offset. The CB formations 450 of the cell 400 are offset on the gates 310. However, process variations may cause the CB formation 450 to overlap onto the CA formation 440, thereby causing errors, such as shorts. As such, the industry lacks an efficient solution to the problem of congestion and errors caused by C-type formation in integrated circuits formed from processing of semiconductor wafers.
The present disclosure may address and/or at least reduce one or more of the problems identified above.